The continuing demand for increasing computational power and memory space is driving the miniaturization of integrated circuits. To sustain progress, miniaturization will soon be driven into the nanometer regime. Unfortunately, conventional devices cannot be scaled down straightforwardly because of problems caused by parasitic resistance, scattering and tunneling, among other things.
Single-electronics offer solutions to some of the problems arising from miniaturization. Single-electronic devices can be made from readily available materials and can use as little as one electron to define a logic state. Unlike conventional devices, single-electron devices show improved characteristics when their feature size is reduced. This follows from the fact that single-electron devices are based on quantum mechanical effects which are more pronounced at smaller dimensions. Single-electron devices also have low power consumption and therefore there are no energy restrictions to exploit the high integration densities that are possible with such devices.
The practical implementation of single-electronic devices has yet to be realized, in part because there is no practical process technology to mass produce nanometer-scale single-electron device structures. Additionally, no process exists for manufacturing single-electronic devices that can be readily combined with present procedures for manufacturing very large scale integrated circuits (VSLI). One reason for the lack of a practical process involves problems in the manufacture of quantum islands and their alignment with other device components.
Quantum islands are a central structural feature of all single-electron devices. Those skilled in the art are familiar with discrete electron tunneling and with other terms used to refer to the quantum island, such as a quantum dot, a grain, a particle or node. The term quantum island as used herein is defined as the structure between contacts, such as a source and drain electrodes. The structure of the quantum island must facilitate the movement of discrete electron tunneling from the source to the quantum island and from the quantum island to the drain.
Conventional methods for forming quantum islands are either impractical or incompatible with existing VSLI process technology. For instance, it is impractical to produce quantum islands in commercial numbers by scanning tunneling microscopy (STM) or atomic force microscopy (AFM). It is also problematic to form quantum islands by using lithographic procedures to select an area of silicon and then performing repeated cycles of etching and oxidation to define the island. The pitch between quantum islands formed in this manner is undesirably large (e.g., center to center distance of greater than 200 nanometers) because of the limits in resolution of existing lithographic technology.
Quantum islands formed by growing germanium, or depositing gold clusters, on silicon substrates suffer from alignment problems. That is, once gold or germanium quantum islands are formed on the substrate, it is very difficult to reproducibly align electrical contacts with the quantum island. This, in turn, makes it difficult to produce single-electron devices with reproducible performance characteristics, and to connect such devices to traditional device components, such as metal oxide semiconductors (MOS) devices.
Accordingly, what is needed in the art is a single-electron device and method of manufacturing thereof that overcomes the above-mentioned problems, and in particular allows for the production of quantum islands that can be easily and reproducibly aligned with contact electrodes.